Thin film transistors, made of amorphous or polycrystalline silicon, or other suitable semiconductor materials, are widely used as low voltage pixel addressing elements in large area, flat panel displays because of their low cost and low processing temperature. Conventional low voltage MOSFET transistors are not capable of sustaining more than 20 or 30 volts before gate-induced junction breakdown occurs, caused by the gate electrode being aligned with or overlapping the drain electrode. It can be observed that when a drain voltage in excess of 20 to 30 volts is applied, leakage current starts to increase, even when the gate voltage (V.sub.G) is zero. Therefore, since the transistor cannot be switched to an OFF condition, the ON/OFF ratio will be very low and the device will have very little practical application as a high voltage logic circuit element. This phenomenon can be seen clearly in curves A (ON) and B (OFF) of FIG. 1 wherein there is shown the operational characteristics of a low voltage transistor in the form of a conventional dual gate device, comparable to that illustrated and described in "MOS Field Effect Transistors and Integrated Circuits" (Richman), at pages 191-193. It should be noted that while device operation is satisfactory when V.sub.G is high (e.g. 30 volts), satisfactory operation is only exhibited at low drain voltages (V.sub.D) when V.sub.G is low (0 volts), for switching OFF the device. The OFF-state leakage current (I.sub.LEAK) starts to increase at a drain voltage of about 25 volts, and the device reaches breakdown, as defined arbitrarily by a leakage current (I.sub.LEAK) of about 10 nA (1E-08) at around 33 volts. At high drain voltages, the leakage current is so high that it is difficult to distinguish between ON and OFF states.
Many applications require drive voltages well in excess of 100 volts, for example, ferroelectric liquid crystal, electrophoretic or PLZT electro-optic displays. The intent in designing a high voltage thin film transistor is to extend the low current regime of low gate voltages (V.sub.G =0) to higher drain voltages, as shown in curve C of FIG. 1. A high voltage thin film transistor capable of sustaining 400 volt, or greater, operation is described in U.S. Pat. No. 4,752,814 (Tuan), entitled "High Voltage Thin Film Transistor" and assigned to the same assignee as this application.
In order to sustain drain bias voltages greater than 60 volts, and as much as several hundred volts, without incurring drain junction breakdown, high voltage thin film transistors require that the drain be offset from the gate. Such devices include, within the active layer, an offset region (L.sub.OFF) of intrinsic or lightly doped semiconductor (n.sup.- or p.sup.-) between the channel region under the gate and the heavily-doped n.sup.+ (or p.sup.+) drain. It is well known that L.sub.OFF is a critical device parameter in offset-gate HVTFTs which influences device performance, so that any variations will change the device characteristics. A large L.sub.OFF increases the drain breakdown voltage V.sub.BD, reduces the current-drive I.sub.D, and worsens the current pinching effects observed under low drain biases. Precise control of L.sub.OFF is especially critical for large-area electronics where the alignment error across a large area substrate can be more severe. Therefore, HVTFT device structures with high alignment accuracy are greatly desirable and of technological importance.
A conventional method for achieving a drain side offset region, L.sub.OFF, (between the n.sup.+ drain and the gate) is illustrated in FIG. 2. Upon substrate 1 there is deposited an active semiconductor layer 2 and a gate dielectric layer 3. A first mask (not shown) defines the placement of gate electrode 4 upon the gate dielectric layer. After the gate 4 has been formed, the active semiconductor layer 2 receives an n.sup.- implant, leaving underlying channel 5 undoped. A second mask 6 establishes the drain offset length L.sub.OFF relative to the gate edge, so that an n.sup.+ implant with the mask in place forms the n.sup.+ source and drain regions 7 and 8. The n.sup.- region 9 defines the drain offset length L.sub.OFF. The degree of accuracy achieved in establishing this length is dependent upon the exactness of alignment between the second mask 6 and the gate mask. It should be understood that this length is very sensitive to misalignments. Furthermore, there is an intrinsic alignment limitation when two masks are used, regardless of the precision exercised by the operator. Although this limitation can be ameliorated by precise alignment tools, which drive up processing time and costs, exact alignment is not possible.
A method which has been suggested for overcoming the misalignment problem is illustrated in FIG. 3. This approach is more fully described in "High-Voltage Silicon Thin Film Transistor on Quartz" authored by Unagami and Tsujiyama, and published in IEEE Electron Device Letters, Vol. EDL-3, No. 6, Jun. 1982, at pages 167-168, and in "Fabrication of High Voltage Polysilicon TFTs on an Insulator" authored by Pennell, Catero and Lovelis, and published in the Journal of the Electrochemical Society: Solid State Science and Technology, Vol. 133, No. 11, Nov. 1986 at pages 2358-2361.
Elements in FIG. 3 similar to those illustrated in FIG. 2 are identified with the same numerals with a prime (') attached. Instead of merely providing an offset region on the drain electrode side of gate 4', n.sup.- offset regions 9' and 9" are located on the source and drain electrode sides by means of a single straddling mask 6'. The rationale for this modification is to use a single offset mask 9, straddling the gate 4' to obtain a constant total offset length (L.sub.source +L.sub.drain =K) irrespective of misalignment errors. A drawback to this approach is that the introduction of source side offset 9' degrades device performance by introducing a series resistance and lowering the device current I.sub.D, but it has only little positive effect upon the breakdown voltage. The single mask 6' is still susceptible to misalignment relative to the gate, but its salutory effect is to improve device-to-device current uniformity across a large area substrate. This is because the benefit achieved by the drain side offset 9" will be balanced by the negative effect of the source side offset 9'. A longer drain side offset decreases I.sub.D as does a longer source side offset, and vice versa. Therefore, since a longer L.sub.drain will be associated with a shorter L.sub.source, and vice versa, misalignments across the substrate will result in a lower absolute value of I.sub.D, because of the introduction of L.sub.source, but the bandwidth of the current uniformity will be narrower than that of the HVTFT fabricated by the FIG. 2 method. Nevertheless, the devices will have a higher breakdown voltage because of the introduction of L.sub.drain.
It is the object of my invention to provide a high voltage thin film transistor having improved uniformity and reproducibility, which includes an offset region of precise length L.sub.OFF only on the drain side of the control gate.
It is another object of my invention to provide a method for fabricating a high voltage thin film transistor which is totally immune to misalignment errors in the formation of an offset region between the control gate and the drain electrode.